The objective of this work is to design the circuit in advanced design system and made the design to printed circuit board. To test the designed printed circuit board using vector network analyzer device.
Signal integrity refers to the quality of the signal that needs to be maintained for the receiver in an electronic design. As the speed of the data signal increases lead to the degradation of the high speed signals. High speed PCB design refers to the techniques that must be followed in order for a circuit on a Printed Circuit Board to function properly when the edge rate and data rate of the signal propagating on the PCB is high. A high edge rate implies a high frequency ]. The failures in high speed circuit are often not readily reproducible. They are often difficult to reproduce and fix. This is unlike the errors in the schematics and layout stage, where, it is possible to check the design using simple rules and instruments. High speed design failures show up as failures at higher operating frequency, data error rates, cross talk errors and EMI errors. The debugging of high speed related errors may need expensive instruments, e.g., high bandwidth oscilloscope, spectrum analyzers, time domain reflectometer, vector network analyzer, to detect and understand the failure mechanism. Therefore, care must be taken at the design stage itself to ensure that the design is in accordance to high speed design rules .
1.1 INTEGRITY OF POINT TO POINT SIGNAL
When a driver gives a signal, it travels along the traces of the PCB. The traces that travel on the PCB must follow certain rules for proper operation at high speed. One of the rules they usually need to follow is that their trace width and their separation above the ground or power plane has a well defined value. These well defined values of the trace width and its separation from power plane make the trace a transmission line. A transmission line is called a micro strip if it is on outer layer. The transmission line is called a strip line, if it is lies on an inner layer sandwiched between metallic layers that can be power or ground layers. If the width of the trace is fixed, and its separation from the ground plane is fixed throughput the duration of the trace, its characteristic impedance stays fixed for the complete length of the trace. Keeping the characteristic impedance constant throughout the duration of the trace is the key to preserving the distortion less signal transmission. Any discontinuity in the characteristic impedance makes a part of the signal reflect at the point of discontinuity. These impedance discontinuities degrade and distort the signal received at the receiver. During it travel on the PCB the signal may also come across the discrete components, which used to ensure proper signal quality. It is the responsibility of the PCB designer to ensure proper placement of these components and proper routing of the traces connecting these components.
1.2 TIMING RELATIONSHIP BETWEEN SIGNALS
The signal given at one end of the PCB trace takes finite amount of time when traveling from one end to another end of the trace. The signal typically takes 150 ps to travel 1 inch of trace. If your trace is 8 inches long, it will take 1200 ps to travel from one end of the trace to the other end. In many buses, clock and data need to preserve a definite timing relationship. If the receiver captures data at the rising edge of the clock, then the data must arrive and become stable slightly before the rising edge of the clock. The time before which the data must be valid before the rising edge of the clock is called setup time. For example, a receiver having a setup time requirement of 1200 ps. It means that the data must arrive at least 1200 ps before the arrival of the clock signal. A transmitter drives data at t = 0 ps and the rising edge of the clock at t = 1500 ps. If the lengths of the data trace and the clock trace are equal on the PCB, data will arrive 1500 ps before the rising edge of the clock. Since the data arrives before the setup time of the clock, it will be correctly captured by the receiver. Now consider an extreme case where data trace is made very long. So long so that it takes data signal 500 ps more than it takes to the clock signal to arrive at the receiver. This means that the receiver sees data signal arriving just 1500 ps – 500 ps = 1000 ps before the clock signal. The receiver, however requires that the data be available and stable at least 1200 ps before the clock signal. The PCB design error like this can lead to the failure to meet set up time requirement of the receiver. This can be a cause of intermittent failure. PCB designers need to ensure that the delay caused in the PCB routing does not lead to the undesirable timing relationship between the clock and the data signals.
1.3 COUPLING OF TRACES
Two nearby traces create coupling. Changing electric field due to the rate of change of voltage dv/dt, on one trace induces a capacitive coupling on a nearby trace. A changing magnetic field due to changing current di/dt on one trace induces inductive coupling on a nearby trace. The capacitive or the inductive coupling induce undesired distortions in the form of cross talk in the nearby traces. A trace carrying higher edge rate signal has the potential to create more cross talk. Keeping high edge rate trace far away helps reduce the cross talk, as does reducing the trace to ground plane separation. So that PCB designers to follow rules to avoid cross talk created due to high speed traces. The task involves identification of high speed traces, calculation of amount of tolerable cross talk, formulation of the rules and adherence to the rules. PCB Designers are often required to keep the design as compact as possible. To reduces the cross talk, on the other hand, it is required that the traces be spread out. It is the job of the PCB designer to balance the contradictory requirements. Identifying the high speed signals, calculating the tolerable crosstalk, forming and following the design rule is the key to designing a PCB free from cross talk errors.
1.4 NOISELESS POWER SUPPLY
All ICs need power supply to operate. The power is supplied to the ICs using power and ground planes and using thick traces connecting to the power and ground pins of the ICs. A number of events lead to fluctuation of voltage level on the power supply and ground nets. One of the reasons can be change in the load current because of the simultaneous switching of the output pins. The noise generated on the power supply may have frequencies from few kHz to several hundred MHz A number of techniques are used to ensure that power supply rail is free from any noise or unwanted fluctuations. This involves use of power and ground plane, proper use and placement of decoupling capacitors. Low ac impedance between power and ground pins of all ICs at all frequencies ensures that the noise on ac rail is shorted to ground. When noise frequency is low, a big bulk capacitor between the power and ground plane removes the low frequency noise. At higher frequencies small decoupling capacitors with low parasitic inductance, placed near the ICs creates low impedance ac path between power and ground planes . At very high frequencies, power and ground planes placed adjacent to each other provide low impedance ac path.
1.5 ELECTROMAGNETIC RADIATION
The PCB traces carrying the high speed signal can be source of radiation. A high edge rate causes more chances of signal radiation. Traces that are not adequately terminated lead to more reflection and higher emission. The clock oscillators are major sources of radiation . The radiation pattern observed in a spectrum analyzer shows frequencies that are usually a multiple or harmonics of clock oscillators used in design. It is impossible to completely suppress the radiation. In PCB design need to follow few design rules to minimize the signal radiation.
If all the five areas of the PCB design along with the circuit design are addressed, the board that is less likely to fail in the lab tests and in field because of the errors, distortion, crosstalk and radiation in the high speed signaling.
1.6 PCB DESIGN
The board design need to spend some time on the signal integrity aspect of the
design. This means that the list of tasks creating footprints, maintaining library, placement, routing, generating Gerber files and creating documentation. The designed schematic, then verifying schematics and note down the nets that need special signal integrity concern from the block diagram of the design. The design involves amplifier. Note down the bandwidth considerations and relative timing requirements. If layout tool has the ability to automatically generate DRC (Design Rule Check) errors based upon the length difference between traces. The schematics to find the most critical nets. Place the components in such a way that it minimizes the length of the high speed nets. If there are two ways to place components, prefer the one that reduces the routing length of the high speed nets.
Most of the high speed nets are required to have a definite value of characteristic impedance (typically 50 ohm). This definite value of characteristic impedance is achieved by routing the signal with a precise value of this width of the signal (5 mils is a typical value) and its separation from the ground and power planes. From schematic will identify all the nets that need a definite desired value of characteristic impedance.
The designs have large number of differential signaling traces. Identify all the differential nets in the design. All differential signals are required to have a definite value of differential impedance. To achieve the required differential impedance by
1.Definite value of width of trace.
2.Definite value of separation between the positive and negative trace.
3.Definite value of separation between the trace and power or ground layers.
1.7 SIGNAL INTEGRITY ISSUES
There are four main areas of circuit design and layout that must be taken into consideration to ensure that the signal integrity of a board or circuit design are maintained:
•Transmission line effects
•Simultaneous switching effects
To ensure that signal integrity is maintained, all the issues must be addressed to ensure that the signal is not distorted in any way and the data is corrupted. In this way the system is able to operate satisfactorily without errors and at the required speed.
1.7.1 Transmission Line Effects
At low frequencies a length of track considered by its DC characteristics. However as frequencies rise, effects including the capacitance and inductance associated with the track start to have a significant impact on the performance of the line. Accordingly it is necessary to consider the tracks as transmission lines, and treat as the line impedance. As a result it is necessary to ensure that the line maintains the same characteristic impedance along the length of the line, otherwise discontinuities will be introduced. This may result in signal reflections being created that may give rise to ringing and poor signal integrity.
In order to ensure the transmission lines are treated correctly. First it is necessary for the lines to have a ground plane underneath them. It is necessary to calculate the impedance of the line. This is determined from a combination of the line thickness, the distance between the line and the ground plane, and the dielectric constant of the board.
1.7.2 Impedance Matching
The PCBs act more like transmission lines as the frequencies increase, so too it is necessary to consider the way in which the impedances need to be matched to ensure good signal integrity. When there is a mismatch between the line and the load, not all the energy of the waveform is absorbed by the load. That which is not absorbed is reflected back along the line where it may again not be absorbed if there is a mismatch between the transmitter and the line. This can cause overshoot and ringing which leads to poor signal integrity and giving rise to signal errors. To overcome this problem it is necessary to match the transmission line to the line drivers or transmitters and the line receivers. If not possible between the transmission line and the receiver, use a resistor down to ground. In this way the parallel combination of the line receiver and the resistor can equal the line impedance.
In some applications, it may be possible to add clamping diodes to reduce the level of overshoot and undershoot, and in this way maintain the levels of signal integrity.
However wherever possible it is far better to ensure that proper matching is achieved.
1.7.3 Simultaneous Switching Effects :
One effect that can disrupt the signal integrity on a circuit board occurs when several output lines are switched simultaneously. As stored charge on the outputs needs to be discharged, this gives rise to high levels of transient currents. While the levels of transients are normally adequate for single outputs changing, if several lines are switched simultaneously, and this can give rise to problems. Problems with signal integrity arise voltage between the device ground and the board ground. To overcome this problem there are a number of measures that can be incorporated. Good grounding is essential: a ground plane must be used to ensure a low resistance ground return.
This aspect of signal integrity arises from the fact that signals appearing on one line appear on nearby lines. This can result in spurious spikes and other signal appearing on nearby lines. This can cause erroneous data or clocking pulses to appear, and these can be very difficult to track down in some circumstances. Poor signal integrity from crosstalk arises from two causes, namely mutual inductance, and mutual capacitance.
The mutual inductance is the effect that is used in transformers. It arises from the fact that a current in one track sets up a magnetic field. Changes in this field then induce a current in a nearby track. Mutual capacitive occurs as a result of the coupling of the electric fields between two tracks. A voltage appearing on one track creates an electric field which can couple to a second line. Changing voltages, especially fast edges can result in similar edges appearing on nearby lines.